x86

Learn to demote specific blocks from L1 data cache to L2 without full hierarchy flush or DRAM writeback. Explore x86 cache instructions, ARM management, RISC-V extensions, cache pollution, and inclusive vs exclusive impacts for cpu caches optimization.

Understand why compilers generate 'sub esp, 8' after stdcall calls but not cdecl in unoptimized x86 assembly. Explains stack frame management, ret 8 vs ret, and calling conventions differences for debugging.